View XC2C64A-5VQG44C_5826346.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ds311 (v2.3) november 19, 2008 www.xilinx.com 1 product specification ? 2004?2008 xilinx, inc. all xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm . all other trademarks and registered trademarks are the property of their respective owners. all specifications are subject to c hange without notice. features ? optimized for 1.8v systems - as fast as 4.6 ns pin-to-pin logic delays - as low as 15 a quiescent current ? industry?s best 0.18 micron cmos cpld - optimized architecture fo r effective logic synthesis - multi-voltage i/o operation ? 1.5v to 3.3v ? available in multiple package options - 44-pin vqfp with 33 user i/os - 48-land qfn with 37 user i/os - 56-ball cp bga with 45 user i/os - 100-pin vqfp with 64 user i/os - pb-free available for all packages ? advanced system features - fastest in system programming 1.8v isp using ieee 1532 (jtag) interface - ieee1149.1 jtag boundary scan test - optional schmitt-trigger input (per pin) - two separate i/o banks - realdigital 100% cmos product term generation - flexible clocking modes optional dualedge triggered registers - global signal options with macrocell control multiple global clocks with phase selection per macrocell multiple global output enables global set/reset - efficient control term clocks, output enables, and set/resets for each macroc ell and shared across function blocks - advanced design security - optional bus-hold, 3-state, or weak pullup on selected i/o pins - open-drain output option for wired-or and led drive - optional configurable grounds on unused i/os - mixed i/o voltages compatible with 1.5v, 1.8v, 2.5v, and 3.3v logic levels - pla architecture superior pinout retention 100% product term routability across function block - hot pluggable refer to the coolrunner?-ii family data sheet for architec- ture description. description the coolrunner-ii 64-macrocell device is designed for both high performance and low power applications. this lends power savings to high-end communication equipment and high speed to battery operated devices. due to the low power stand-by and dynamic operation, overall system reli- ability is improved. this device consists of four function blocks inter-connected by a low power advanced interconnect matrix (aim). the aim feeds 40 true and complement inputs to each function block. the function blocks consist of a 40 by 56 p-term pla and 16 macrocells which contain numerous configura- tion bits that allow for combinational or registered modes of operation. additionally, these registers can be globally reset or preset and configured as a d or t flip-flop or as a d latch. there are also multiple clock signals, both global and local product term types, configured on a per macrocell basis. output pin configurations include slew rate limit, bus hold, pull-up, open drain, and programmable grounds. a schmitt trigger input is available on a per input pin basis. in addition to stor- ing macrocell output states, the macrocell registers can be configured as "direct input" registers to store signals directly from input pins. clocking is available on a global or function block basis. three global clocks are available for all function blocks as a synchronous clock source. macrocell registers can be indi- vidually configured to power up to the zero or one state. a global set/reset cont rol line is also available to asynchro- nously set or reset selected registers during operation. additional local clock, synchronous clock-enable, asynchro- nous set/reset, and output enable signals can be formed using product terms on a per-macrocell or per-function block basis. a dualedge flip-flop feature is also available on a per mac- rocell basis. this feature allows high performance synchro- nous operation based on lower frequency clocking to help reduce the total power consumption of the device. the coolrunner-ii 64-macroce ll cpld is i/o compatible with standard lvttl and lvcmos18, lvcmos25, and lvcmos33 (see ta b l e 1 ). this device is also 1.5v i/o com- patible with the use of schmitt-trigger inputs. another feature that eases voltage translation is i/o bank- ing. two i/o banks are available on the coolrunner-ii 64a macrocell device that permit easy interfacing to 3.3v, 2.5v, 1.8v, and 1.5v devices. 0 xc2c64a coolrunner-ii cpld ds311 (v2.3) november 19, 2008 00 product specification r
xc2c64a coolrunner-ii cpld 2 www.xilinx.com ds311 (v2.3) november 19, 2008 product specification r realdigital design technology xilinx? coolrunner-ii cplds are fabricated on a 0.18 micron process technology which is derived from lead- ing edge fpga product development. coolrunner-ii cplds employ realdigital, a design techniq ue that makes use of cmos technology in both the fabrication and design methodology. realdigital design technology employs a cas- cade of cmos gates to implement sum of products instead of traditional sense amplifier methodology. due to this tech- nology, xilinx coolrunner-ii cplds achieve both high per- formance and low power operation. supported i/o standards the coolrunner-ii 64 macrocell features both lvcmos and lvttl i/o implementations. see ta bl e 1 for i/o stan- dard voltages. the lvttl i/o standard is a general purpose eia/jedec standard for 3.3v applications that use an lvttl input buffer and push-pull output buffer. the lvcmos standard is used in 3.3v, 2.5v, and 1.8v applica- tions. coolrunner-ii cplds are also 1.5v i/o compatible with the use of schmitt-trigger inputs. ta b l e 1 : i/o standards for xc2c64a iostandard attribute output v ccio input v ccio input v ref board termination voltage v t lvttl 3.3 3.3 n/a n/a lvcmos33 3.3 3.3 n/a n/a lvcmos25 2.5 2.5 n/a n/a lvcmos18 1.8 1.8 n/a n/a lv c m o s 1 5 (1) 1.5 1.5 n/a n/a 1. lvcmos15 requires schmitt-trigger inputs. figure 1: i cc vs frequency ta bl e 2 : i cc vs frequency (lvcmos 1.8v t a = 25c) (1) frequency (mhz) 0 25 50 75 100 150 175 200 225 240 typical i cc (ma) 0.017 1.8 3.7 5.5 7.48 11.0 12.7 14.6 15.3 17.77 notes: 1. 16-bit up/down, resetable binary c ounter (one counter per function block). frequency (mhz) ds092_01_092302 i cc (ma) 0 0 10 5 15 20 250 200 150 100 50
xc2c64a coolrunner-ii cpld ds311 (v2.3) november 19, 2008 www.xilinx.com 3 product specification r recommended operating conditions dc electrical characteristics over recommended operating conditions absolute maximum ratings symbol description value units v cc supply voltage relative to ground ?0.5 to 2.0 v v ccio supply voltage for output drivers ?0.5 to 4.0 v v jtag (2) jtag input voltage limits ?0.5 to 4.0 v v ccaux jtag input supply voltage ?0.5 to 4.0 v v in (1) input voltage relative to ground (1) ?0.5 to 4.0 v v ts (1) voltage applied to 3-state output (1) ?0.5 to 4.0 v v stg (3) storage temperature (ambient) ?65 to +150 c t j junction temperature +150 c notes: 1. maximum dc undershoot below gnd must be li mited to either 0.5v or 10 ma, whichever is easiest to achieve. during transitions, the device pins might undershoot to ?2.0v or overshoot to +4.5 v, provided this overshoot or undershoot lasts less than 10 ns and with the forcing current being limited to 200 ma. 2. valid over commercial temperature range. 3. for soldering guidelines and thermal considerations, see the device packaging information on the xilinx website. for pb free packages, see xapp427 . symbol parameter min max units v cc supply voltage for internal logic and input buffers commercial t a = 0c to +70c 1.7 1.9 v industrial t a = ?40c to +85c 1.7 1.9 v v ccio supply voltage for output drivers @ 3.3v operation 3.0 3.6 v supply voltage for output drivers @ 2.5v operation 2.3 2.7 v supply voltage for output drivers @ 1.8v operation 1.7 1.9 v supply voltage for output drivers @ 1.5v operation 1.4 1.6 v v ccaux jtag programming pins 1.7 3.6 v symbol parameter test conditions typical max. units i ccsb standby current commercial v cc = 1.9v, v ccio = 3.6v 31 100 a i ccsb standby current industrial v cc = 1.9v, v ccio = 3.6v 43 165 a i cc (1) dynamic current f = 1 mhz - 500 a f = 50 mhz - 5 ma c jtag jtag input capacitance f = 1 mhz - 10 pf c clk global clock input capacitance f = 1 mhz - 12 pf c io i/o capacitance f = 1 mhz - 10 pf i il (2) input leakage current v in = 0v or v ccio to 3.9v - +/?1 a i ih (2) i/o high-z leakage v in = 0v or v ccio to 3.9v - +/?1 a notes: 1. 16-bit up/down, resetable binary counter (one counter per function block) tested at v cc =v ccio = 1.9v. 2. see quality and reliability section of the coolrunner-ii family data sheet.
xc2c64a coolrunner-ii cpld 4 www.xilinx.com ds311 (v2.3) november 19, 2008 product specification r lvcmos 3.3v and lvttl 3.3v dc voltage specifications lvcmos 2.5v dc voltage specifications lvcmos 1.8v dc voltage specifications symbol parameter test conditions min. max. units v ccio input source voltage 3.0 3.6 v v ih high level input voltage 2 3.9 v v il low level input voltage ?0.3 0.8 v v oh high level output voltage i oh = ?8 ma, v ccio = 3v v ccio ? 0.4v - v i oh = ?0.1 ma, v ccio = 3v v ccio ? 0.2v - v v ol low level output voltage i ol = 8 ma, v ccio = 3v - 0.4 v i ol = 0.1 ma, v ccio = 3v - 0.2 v symbol parameter test conditions min. max. units v ccio input source voltage 2.3 2.7 v v ih high level input voltage 1.7 v ccio + 0.3 (1) v v il low level input voltage ?0.3 0.7 v v oh high level output voltage i oh = ?8 ma, v ccio = 2.3v v ccio ? 0.4v - v i oh = ?0.1 ma, v ccio = 2.3v v ccio ? 0.2v - v v ol low level output voltage i ol = 8 ma, v ccio = 2.3v - 0.4 v i ol = 0.1 ma, v ccio = 2.3v - 0.2 v 1. the vih max value represents the jedec sp ecification for lvcmos25. the coolrunner-ii cpld input buffer can tolerate up to 3.9 v without physical damage. symbol parameter test conditions min. max. units v ccio input source voltage - 1.7 1.9 v v ih high level input voltage - 0.65 x v ccio v ccio + 0.3 (1) v v il low level input voltage - ?0.3 0.35 x v ccio v v oh high level output voltage i oh = ?8 ma, v ccio = 1.7v v ccio ? 0.45 - v i oh = ?0.1 ma, v ccio = 1.7v v ccio ? 0.2 - v v ol low level output voltage i ol = 8 ma, v ccio = 1.7v - 0.45 v i ol = 0.1 ma, v ccio = 1.7v - 0.2 v 1. the v ih max value represents the jedec specificat ion for lvcmos18. the coolrunner-ii cpld input buffer can tolerate up to 3.9v without physical damage.
xc2c64a coolrunner-ii cpld ds311 (v2.3) november 19, 2008 www.xilinx.com 5 product specification r lv c m o s 1.5v dc voltage specifications schmitt trigger input dc voltage specifications symbol parameter (1) test conditions min. max. units v ccio input source voltage - 1.4 1.6 v v t+ input hysteresis threshold voltage - 0.5 x v ccio 0.8 x v ccio v v t- -0.2 x v ccio 0.5 x v ccio v v oh high level output voltage i oh = ?8 ma, v ccio = 1.4v v ccio ? 0.45 - v i oh = ?0.1 ma, v ccio = 1.4v v ccio ? 0.2 - v v ol low level output voltage i ol = 8 ma, v ccio = 1.4v - 0.4 v i ol = 0.1 ma, v ccio = 1.4v - 0.2 v notes: 1. hysteresis used on 1.5v inputs. symbol parameter test conditions min. max. units v ccio input source voltage - 1.4 3.9 v v t+ input hysteresis threshold voltage - 0.5 x v ccio 0.8 x v ccio v v t- -0.2 x v ccio 0.5 x v ccio v
xc2c64a coolrunner-ii cpld 6 www.xilinx.com ds311 (v2.3) november 19, 2008 product specification r ac electrical characteristics over recommended operating conditions symbol parameter -5 -7 units min. max. min. max. t pd1 propagation delay single p-term - 4.6 - 6.7 ns t pd2 propagation delay or array - 5.0 - 7.5 ns t sud direct input register clock setup time 2.4 - 3.3 - ns t su1 setup time (single p-term) 2.0 - 2.5 - ns t su2 setup time (or array) 2.4 - 3.3 - ns t hd direct input register hold time 0 - 0 - ns t h p-term hold time 0 - 0 - ns t co clock to output - 3.9 - 6.0 ns f toggle (1) internal toggle rate (1) -500-300mhz f system1 (2) maximum system frequency (2) -263-159mhz f system2 (2) maximum system frequency (2) -238-141mhz f ext1 (3) maximum external frequency (3) -169-118mhz f ext2 (3) maximum external frequency (3) -159-108mhz t psud direct input register p-term clock setup time 0.9 - 1.7 - ns t psu1 p-term clock setup time (single p-term) 0.6 - 0.9 - ns t psu2 p-term clock setup time (or array) 1.0 - 1.7 - ns t phd direct input register p-term clock hold time 1.3 - 1.4 - ns t ph p-term clock hold 1.5 - 1.7 - ns t pco p-term clock to output - 6.0 - 8.4 ns t oe /t od global oe to output enable/disable - 8.0 - 10.0 ns t poe /t pod p-term oe to output enable/disable - 9.0 - 11.0 ns t moe /t mod macrocell driven oe to output enable/disable - 9.0 - 11.0 ns t pao p-term set/reset to output valid - 7.3 - 9.7 ns t ao global set/reset to output valid - 6.0 - 8.3 ns t suec register clock enable setup time 3.0 - 3.7 - ns t hec register clock enable hold time 0 - 0 - ns t cw global clock pulse width high or low 1.4 - 2.2 - ns t pcw p-term pulse width high or low 5.0 - 7.5 - ns t aprpw asynchronous preset/reset pulse width (high or low) 5.0 - 7.5 - ns t config (4) configuration time - 50.0 - 50.0 s notes: 1. f toggle is the maximum frequency of a dual edge triggered t flip-flop with output enabled. 2. f system (1/t cycle ) is the internal operating frequency for a device full y populated with 16-bit up/down, resetable binary counter (one counter per function block). 3. f ext (1/t su1 +t co ) is the maximum external frequency. 4. typical configuration current during t config is 2.3 ma.
xc2c64a coolrunner-ii cpld ds311 (v2.3) november 19, 2008 www.xilinx.com 7 product specification r internal timing parameters symbol parameter (1) -5 -7 units min. max. min. max. buffer delays t in input buffer delay - 1.7 - 2.4 ns t din direct data register input delay - 2.6 - 4.0 ns t gck global clock buffer delay - 1.6 - 2.5 ns t gsr global set/reset buffer delay - 2.4 - 3.5 ns t gts global 3-state buffer delay - 2.7 - 3.9 ns t out output buffer delay - 1.9 - 2.8 ns t en output buffer enable/disable delay - 5.3 - 6.1 ns p-term delays t ct control term delay - 2.0 - 2.5 ns t logi1 single p-term delay adder - 0.5 - 0.8 ns t logi2 multiple p-term delay adder - 0.4 - 0.8 ns macrocell delay t pdi input to output valid - 0.5 - 0.7 ns t sui setup before clock 1.4 - 1.8 - ns t hi hold after clock 0.0 - 0.0 - ns t ecsu enable clock setup time 0.9 - 1.3 - ns t echo enable clock hold time 0 - 0 - ns t coi clock to output valid - 0.4 - 0.7 ns t aoi set/reset to output valid - 1.7 - 2.0 ns t cdbl clock doubler delay - 0 - 0 ns feedback delays t f feedback delay - 1.5 - 3.0 ns t oem macrocell to global oe delay - 1.7 - 1.7 ns i/o standard time adder delays 1.5v cmos t hys15 hysteresis input adder - 4.0 - 6.0 ns t out15 output adder - 0.9 - 1.5 ns t slew15 output slew rate adder - 4.0 - 6.0 ns i/o standard time adder delays 1.8v cmos t hys18 hysteresis input adder - 3.0 - 4.0 ns t out18 output adder - 0 - 0 ns t slew output slew rate adder - 3.5 - 5.0 ns
xc2c64a coolrunner-ii cpld 8 www.xilinx.com ds311 (v2.3) november 19, 2008 product specification r i/o standard time adder delays 2.5v cmos t in25 standard input adder - 0.5 - 0.6 ns t hys25 hysteresis input adder - 2.5 - 3.0 ns t out25 output adder - 0.8 - 0.9 ns t slew25 output slew rate adder - 4.0 - 5.0 ns i/o standard time adder delays 3.3v cmos/ttl t in33 standard input adder - 0.5 - 0.6 ns t hys33 hysteresis input adder - 2.0 - 3.0 ns t out33 output adder - 1.2 - 1.4 ns t slew33 output slew rate adder - 4.0 - 5.0 ns 1. 1.5 ns input pin signal rise/fall. internal timing parameters (continued) symbol parameter (1) -5 -7 units min. max. min. max.
xc2c64a coolrunner-ii cpld ds311 (v2.3) november 19, 2008 www.xilinx.com 9 product specification r switching characteristics ac test circuit typical i/o output curves figure 4: typical i/o output curves figure 2: derating curve for t pd figure 3: ac load circuit number of outputs switching 12 4 8 16 3.0 4.0 5.0 v cc = v ccio = 1.8v, t = 25 o c t pd2 (ns) 5.5 4.5 3.5 ds092_02_092302 r 1 v cc c l r 2 de v ice under test output type lvttl33 lvcmos33 lvcmos25 lvcmos1 8 lvcmos15 r 1 26 8 275 1 88 112.5 150 r 2 235 275 1 88 112.5 150 c l 35 pf 35 pf 35 pf 35 pf 35 pf ds311_03_10210 8 test point notes: 1. c l incl u des test fixt u res and pro b e capacitance. 2. 1.5 ns maxim u m rise/fall times on inp u ts. vo output volts i/o output current (ma) vdde1 1.5v 1.8v 2.5v 3.3v
xc2c64a coolrunner-ii cpld 10 www.xilinx.com ds311 (v2.3) november 19, 2008 product specification r pin descriptions function block macrocell pc44 (1) vq44 qfg48 cp56 vq100 i/o banking 11 44 38 f1 13 bank 2 12 43 37 5 e3 12 bank 2 13 42 36 4 e1 11 bank 2 14 - - - 10 bank 2 15 - --9bank 2 16 - --8bank 2 17 - --7bank 2 18 - --6bank 2 1(gts1) 9 40 34 2 d1 4 bank 2 1(gts0) 10 39 33 1 c1 3 bank 2 1(gts3) 11 38 32 48 a3 2 bank 2 1(gts2) 12 37 31 47 a2 1 bank 2 1(gsr) 13 36 30 46 b1 99 bank 2 114 - -a197bank 2 115 - -c394bank 2 116 - - - 92 bank 2 21 1 39 6 g1 14 bank 1 22 2 40 7 f3 15 bank 1 23 - -8-16 bank 1 24 - -9-17 bank 1 25 3 41 10 h1 18 bank 1 26 4 42 g3 19 bank 1 2(gck0) 7 5 43 11 j1 22 bank 1 2(gck1) 8 6 44 12 k1 23 bank 1 29 - -k424bank 1 2(gck2) 10 7 113k227 bank 1 211 - - - 28 bank 1 212 8 214k329 bank 1 213 9 315h330 bank 1 214 - -k532bank 1 215 - - - 33 bank 1 216 - - - 34 bank 1
xc2c64a coolrunner-ii cpld ds311 (v2.3) november 19, 2008 www.xilinx.com 11 product specification r 31 35 29 45 c4 91 bank 2 32 34 28 44 a4 90 bank 2 33 33 27 43 c5 89 bank 2 34 - -a781bank 2 35 - -39c879 bank 2 36 29 23 38 a8 78 bank 2 37 - -a977bank 2 38 - - - 76 bank 2 39 - -37a574 bank 2 310 28 22 36 a10 72 bank 2 311 27 21 35 b10 71 bank 2 312 26 20 34 c10 70 bank 2 313 - -d868bank 2 314 25 19 33 e8 67 bank 2 315 24 18 32 d10 64 bank 2 316 - - - 61 bank 2 41 11 517k635 bank 1 42 12 618h536 bank 1 43 - -k737bank 1 44 - - - 39 bank 1 45 - -h740bank 1 46 - - - 41 bank 1 47 14 820h842 bank 1 48 - - - 43 bank 1 49 - - - 49 bank 1 410 - -24k850 bank 1 411 18 12 25 h10 52 bank 1 412 - - 26 - 53 bank 1 413 19 13 27 g10 55 bank 1 414 20 14 28 - 56 bank 1 415 22 16 f10 58 bank 1 416 - - 30 e10 60 bank 1 1. this is an obsolete package type. it remains here for legacy support only. 2. gts = global output enable, gsr = global set reset, gck = global clock. 3. gck, gsr, and gts pins can also be used for general purpose i/os. pin descriptions (continued) function block macrocell pc44 (1) vq44 qfg48 cp56 vq100 i/o banking
xc2c64a coolrunner-ii cpld 12 www.xilinx.com ds311 (v2.3) november 19, 2008 product specification r xc2c64a global, jtag, powe r/ground, and no connect pins ordering information pin type pc44 (1) vq44 qfg48 cp56 vq100 tck 171123 k10 48 tdi 15 9 21 j10 45 tdo 302440 a6 83 tms 161022 k9 47 v ccaux (jtag supply voltage) 41 35 3 d3 5 power internal (v cc ) power bank 1 i/o (v ccio1 ) power bank 2 i/o (v ccio2 ) 21 15 29 g8 26,57 13 7 19 h6 38, 51 32 26 42 c6 88, 98 ground 10, 23, 31 4,17,25 16, 31, 41 h4, f8, c7 21, 31, 62, 69, 84,100 no connects 20, 25, 44, 46, 54, 59, 63, 65, 66, 73, 75, 80, 82, 85, 86, 87, 93, 95, 96 total user i/o 33 33 37 45 64 1. this is an obsolete package type. it remains here for legacy support only. device ordering no. and part marking no. pin/ball spacing ja (c/watt) jc ({c/watt) package type package body dimensions i/o comm(c) ind. (i) (1) xc2c64a-5qfg48c 0.5mm 31.2 21.2 quad flat no lead 7mm x 7mm 37 c xc2c64a-7qfg48c 0.5mm 31.2 21.2 quad flat no lead 7mm x 7mm 37 c xc2c64a-5vq44c 0.8mm 46.6 8.2 very thin quad flat pack 10mm x 10mm 33 c xc2c64a-7vq44c 0.8mm 46.6 8.2 very thin quad flat pack 10mm x 10mm 33 c xc2c64a-5cp56c 0.5mm 65.0 15.0 chip scale package 6mm x 6mm 45 c xc2c64a-7cp56c 0.5mm 65.0 15.0 chip scale package 6mm x 6mm 45 c xc2c64a-5vq100c 0.5mm 53.2 14.6 very thin quad flat pack 14mm x 14mm 64 c xc2c64a-7vq100c 0.5mm 53.2 14.6 very thin quad flat pack 14mm x 14mm 64 c XC2C64A-5VQG44C 0.8mm 46.6 8.2 very thin quad flat pack; pb-free 10mm x 10mm 33 c xc2c64a-7vqg44c 0.8mm 46.6 8.2 very thin quad flat pack; pb-free 10mm x 10mm 33 c xc2c64a-5cpg56c 0.5mm 65.0 15.0 chip scale package; pb-free 6mm x 6mm 45 c xc2c64a-7cpg56c 0.5mm 65.0 15.0 chip scale package; pb-free 6mm x 6mm 45 c xc2c64a-5vqg100c 0.5mm 53.2 14.6 very thin quad flat pack; pb-free 14mm x 14mm 64 c xc2c64a-7vqg100c 0.5mm 53.2 14.6 very thin quad flat pack; pb-free 14mm x 14mm 64 c xc2c64a-7vq44i 0.8mm 46.6 8.2 very thin quad flat pack 10mm x 10mm 33 i xc2c64a-7qfg48i 0.5mm 31.2 21.2 quad flat no lead; pb-free 7mm x 7mm 37 i xc2c64a-7cp56i 0.5mm 65.0 15.0 chip scale package 6mm x 6mm 45 i xc2c64a-7vq100i 0.5mm 53.2 14.6 very thin quad flat pack 14mm x 14mm 64 i
xc2c64a coolrunner-ii cpld ds311 (v2.3) november 19, 2008 www.xilinx.com 13 product specification r device part marking figure 5: sample package with part marking note: due to the small size of chip scale and quad flat no lead packages, the complete ordering part number cannot be included on the package marking. part marking on chip scale and quad flat no lead packages by line are: 1. x (xilinx logo) then truncated part number 2. not related to device part number 3. not related to device part number 4. device code, speed, operating temperature, three digits not related to device part number. device codes: c3 = cp56, c4 = cpg56, q2 = qfg48. xc2c64a-7vqg44i 0.8mm 46.6 8.2 very thin quad flat pack; pb-free 10mm x 10mm 33 i xc2c64a-7cpg56i 0.5mm 65.0 15.0 chip scale package; pb-free 6mm x 6mm 45 i xc2c64a-7vqg100i 0.5mm 53.2 14.6 very thin quad flat pack; pb-free 14mm x 14mm 64 i notes: 1. c = commercial (t a = 0c to +70c); i = industrial (t a = ?40c to +85c). device ordering no. and part marking no. pin/ball spacing ja (c/watt) jc ({c/watt) package type package body dimensions i/o comm(c) ind. (i) (1) standard example: xc2c128 device speed grade package type number of pins temperature range -4 tq c 144 pb- free example: xc2c128 tq g 144 c device speed grade package type pb -free number of pins -4 temperature range xc2cxxx tq144 7c de v ice type package speed operating range this line not related to de v ice part n u m b er r part marking for non-chip scale package ds311_05_10210 8
xc2c64a coolrunner-ii cpld 14 www.xilinx.com ds311 (v2.3) november 19, 2008 product specification r package pinout diagrams figure 6: vq44 package figure 7: pc44 package (obsolete package shown for legacy support only) vq44 top view i/o (1) i/o (1) i/o (1) i/o (3) i/o i/o i/o v ccio2 gnd tdo i/o i/o (2) i/o (2) i/o i/o i/o i/o i/o i/o i/o v aux i/o (1) i/o i/o i/o v cc i/o gnd i/o i/o i/o i/o i/o i/o (2) i/o i/o gnd i/o i/o v ccio1 i/o tdi tms tck 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 33 32 31 30 29 28 27 26 25 24 23 44 43 42 41 40 39 38 37 36 35 34 (1) - global output enable (2) - global clock (3) - global set/reset pc44 top view i/o (1) i/o (1) i/o (1) i/o (3) i/o i/o i/o v ccio2 gnd tdo i/o i/o (2) i/o (2) i/o i/o i/o i/o i/o i/o i/o v aux i/o (1) i/o i/o i/o v cc i/o gnd i/o i/o i/o i/o i/o i/o (2) i/o i/o gnd i/o i/o v ccio1 i/o tdi tms tck 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 39 38 37 36 35 34 33 32 31 30 29 6 5 4 3 2 1 44 43 42 41 40 (1) - global output enable (2) - global clock (3) - global set/reset figure 8: qfg48 package figure 9: cp56 package qfg48 top view i/o i/o i/o i/o i/o gnd i/o vcc i/o i/o i/o i/o i/o (1) i/o (1) i/o(3) i/o i/o i/o vccio2 gnd tdo i/o i/o i/o i/o (2) i/o i/o gnd i/o i/o vccio1 i/o tdi tms tck i/o i/o(1) i/o(1) vaux i/o i/o i/o i/o i/o i/o i/o i/o(2) i/o(2) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 36 35 34 33 32 31 30 29 28 27 26 25 48 47 46 45 44 43 42 41 40 39 38 37 (1) - global output enable (2) - global clock (3) - global set/reset cp56 bottom view i/o (2) i/o (2) i/o i/o i/o i/o i/o i/o tms tck i/o (2) tdi i/o i/o gnd i/o v ccio1 i/o i/o i/o i/o i/o v cc i/o i/o i/o gnd i/o i/o i/o i/o i/o i/o (1) v aux i/o i/o i/o (1) i/o i/o i/o v ccio2 gnd i/o i/o i/o (3) i/o i/o i/o (1) i/o (1) i/o i/o tdo i/o i/o i/o i/o k j h g f e d c b a 1 2 3 4 5 6 7 8 9 10 (1) - global output enable (2) - global clock (3) - global set/reset
xc2c64a coolrunner-ii cpld ds311 (v2.3) november 19, 2008 www.xilinx.com 15 product specification r warranty disclaimer these products are subject to the terms of the xilinx limited warranty which can be viewed at http://www.xilinx.com/warranty.htm . this limited warranty does not extend to any use of the products in an application or environment that is not within the specifications stated on the then-current xilinx data sheet for the products. products are not designed to be fail-safe and are not warranted for use in applications that pose a risk of physical harm or loss of life. use of products in such applications is fully at the risk of customer subject to applicable laws and regulations. figure 12: vq100 package vq100 top view gnd i/o (3) v ccio2 i/o nc nc i/o nc i/o i/o i/o i/o v ccio2 nc nc nc gnd tdo nc i/o nc i/o i/o i/o i/o v cc i/o (2) i/o i/o i/o gnd i/o i/o i/o i/o i/o i/o v ccio1 i/o i/o i/o i/o i/o nc tdi nc tms tck i/o i/o nc i/o nc i/o i/o i/o gnd i/o i/o nc nc i/o nc gnd i/o i/o nc i/o vcc i/o i/o nc i/o i/o v ccio1 i/o (1) i/o (1) i/o (1) i/o (1) v aux i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o nc gnd i/o (2) i/o (2) i/o nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 (1) - global output enable (2) - global clock (3) - global set/reset
xc2c64a coolrunner-ii cpld 16 www.xilinx.com ds311 (v2.3) november 19, 2008 product specification r additional information additional information is available for the following coolrunner-ii cpld topics at www.xilinx.com/support/docum entation/coolrunner-ii.htm : ? device pinouts in the density specific data sheets ? termination, power sequencing, voltage thresholds, and slew rate data in the cpld io user guide ? reliability data in the device reliability report ? packaging thermal and electrical data in the device package user guide package drawings and dimensions are available at: www.xilinx.com/support/documentation/package_specifications.htm revision history the following table shows the revision history for this document. date version revision 5/15/04 1.0 initial xilinx release. 8/30/04 1.1 pb-free documentation 10/01/04 1.2 add asynchronous preset/reset pulse widt h specification to ac electrical characteristics. 11/08/04 1.3 product release. no change to documentation. 11/29/04 1.4 change to qfg package drawing (figure 8). pin 29 relabelled. 12/14/04 1.5 changes to figure 4, typical i/o output curves; changes to t out25 and t out33 , internal timing parameters, page 8. 01/18/05 1.6 changes to i ccsb , f toggle , t psu1 , t psu2 , t phd , t cw , t slew25 , and t slew33 03/07/05 1.7 format change to specifications i il and i ih , page 3. improvement to pin-to-pin logic delay, page 1. modifications to table 1, iostandards. 06/28/05 1.8 move to product specification. change to t in25 , t out25 , t in33 , and t out33 . 01/30/06 1.9 modified footnote 1 from ac specifications table to remove incorrect equation. 03/20/06 2.0 add warranty disclaimer. add note to pin descriptions that gck, gsr, and gts pins can also be used for general purpose i/o. 02/15/07 2.1 change to v ih specification for 2.5v and 1.8v lvcmos. change t f specification on -7 speed grade from 2.0 to 3.0 ns. 03/08/07 2.2 fixed typo in note for v il for lvcmos18; removed note for v il for lvcmos33. 11/19/08 2.3 added note to pin description tables to indicate the pc44 packages are obsolete. removed part numbers for devices in pc44 packages the features section and from the ordering information. see product discontinuation notice xcn07022.pdf .

▲Up To Search▲

Price & Availability of XC2C64A-5VQG44C

	To Download XC2C64A-5VQG44C Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .